1. Field of the Invention
The present invention relates to a voltage adder/subtractor circuit and more particularly, to a voltage adder/subtractor circuit performing addition or subtraction of two input voltages, which has two differential pairs of bipolar or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETS) and which is formed on a semiconductor integrated circuit (IC).
2. Description of the Prior Art
FIG. 1 shows a conventional bipolar voltage adder circuit.
In FIG. 1, a first differential pair is formed by npn bipolar transistors Q101 and Q102 whose emitters are coupled together. The emitters of the transistors Q101 and Q102 are the same in size and therefore, the first differential pair is a balanced emitter-coupled transistor pair.
The coupled emitters of the transistors Q101 and Q102 are connected to a terminal of a constant current sink 101 sinking a constant current I.sub.0. The other terminal of the current sink 101 is connected to the ground. The first differential pair of the transistors Q101 and Q102 is driven by the constant current I.sub.0.
Bases of the transistors Q101 and Q102 are connected to a pair of input terminals T101 and T102, respectively. A first input voltage V.sub.1 is differentially applied across the bases of the transistors Q101 and Q102 through the pair of input terminals T101 and T102. The polarity of the voltage V.sub.1 is defined as positive when the electrical potential at the terminal T101 is higher than that at the terminal T102.
Diode-connected pnp bipolar transistors Q105 and Q107 are connected to the transistors Q101 and Q102 as their loads, respectively. A base and a collector of the transistor Q105 are coupled together to be connected to a collector of the transistor Q101. An emitter of the transistor Q105 is connected to a power supply (not shown) supplying a constant dc voltage V.sub.cc. A base and a collector of the transistor Q107 are coupled together to be connected to a collector of the transistor Q102. An emitter of the transistor Q107 is connected to the power supply.
A second differential pair is formed by npn bipolar transistors Q103 and Q104 whose emitters are coupled together. The emitters of the transistors Q103 and Q104 are the same in size as those of the transistors Q101 and Q102 and therefore, the second differential pair is also a balanced emitter-coupled transistor pair.
The coupled emitters of the transistors Q103 and Q104 are connected to a terminal of a constant current sink 102 sinking the same constant current I.sub.0 as that of the constant current sink 101. The other terminal of the current sink 102 is connected to the ground. The second differential pair of the transistors Q103 and Q104 is driven by the same constant current I.sub.0 as that of the first differential pair.
A base and a collector of the transistor Q103 are coupled together, i.e., the transistors Q103 has a diode-connection. The coupled base and collector of the transistor Q103 are connected to an output terminal T103. An output voltage V.sub.0 is derived from the coupled base and collector of the transistor Q103 through the output terminal T103. The polarity of the voltage V.sub.0 is defined as positive when the electrical potential at the terminal T103 is higher than that at the ground.
A base of the transistor Q104 is connected to an input terminal T104. A second input voltage V.sub.2 is applied to the base of the transistor Q104 through the input terminal T104. The polarity of the voltage V.sub.2 is defined as positive when the electrical potential at the terminal T104 is higher than that at the ground.
A pnp bipolar transistor Q106 is connected to the transistor Q103 at its load. A collector of the transistor Q106 is connected to the coupled collector and base of the transistor Q103. An emitter of the transistor Q105 is connected to the power supply. A base of the transistor Q106 is connected to the coupled base and collector of the transistor Q105 in the first differential pair, thereby constituting a current mirror circuit. This current mirror circuit makes a collector current of the transistor Q101 to be equal to a collector current of the transistor Q103.
A diode-connected pnp bipolar transistor Q108 is connected to the transistor Q104 as its load. A base and a collector of the transistor Q108 are coupled together to be connected to a collector of the transistor Q104. An emitter of the transistor Q108 is connected to the power supply.
The diode-connected transistors Q107 and Q108 are inserted for the purpose of making the voltages at the collectors of the transistors Q102 and Q104 equal with those at the collectors of the transistors Q101 and Q103. Thus, the operating characteristic matching for the first and second differential pairs is improved.
Ignoring the base-width modulation due to the Early effect, a collector current I.sub.c and a base-to-emitter voltage V.sub.BB of a bipolar transistor have, in general, the following relationship (1). ##EQU1##
In the equation (1), V.sub.T and I.sub.s are the thermal voltage and the saturation current of a bipolar transistor, respectively. The thermal voltage V.sub.T is defined as V.sub.T =(kT)/q!, where k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron.
Here, the following circuit analysis is made on the supposition that the dc common-base current gain factor .alpha..sub.F is set as unity (i.e., .alpha..sub.F =1) and thus, no base current flows through the transistor for the sake of the simplification of description.
Using the above relationship (1), collector currents I.sub.C1, I.sub.C2, I.sub.C3, and I.sub.C4 of the transistors Q101, Q102, Q103, and Q104 are expressed as the following equations (2), (3), (4), and (5), respectively. ##EQU2##
Since the collector of the transistor Q101 is connected to the collector of the transistor Q103 through the current mirror circuit formed by the transistors Q105 and Q106, the following equation (6) is established. EQU I.sub.C1 =I.sub.C3 ( 6)
The equation (6) means that the right side of the equation (2) is equal to the right side of the equation (4), resulting in a relationship of V.sub.1 =V.sub.0 -V.sub.2.
Consequently, the following equation (7) is obtained. EQU V.sub.0 =V.sub.1 +V.sub.2 ( 7)
The equation (7) indicates that the output voltage V.sub.0 is equal to the sum of the first and second input voltages V.sub.1 and V.sub.2. Thus, it is seen that the circuit shown in FIG. 1 has a function of adding the two input voltages V.sub.1 and V.sub.2.
FIG. 2 shows a conventional MOS voltage subtractor circuit.
In FIG. 2, a first differential pair is formed by n-channel MOSFETs M101 and M102 whose sources are coupled together. The gate-width (W) to gate-length (L) ratio (W/L) of the MOSFETs M101 and M102 are the same and therefore, the first differential pair is a balanced source-coupled transistor pair.
The coupled sources of the MOSFETs M101 and M102 are connected to a terminal of a constant current sink 111 sinking a constant current I.sub.0. The other terminal of the current sink 111 is connected to the ground. The first differential pair of the MOSFETs M101 and M102 is driven by the constant current I.sub.0.
Gates of the MOSFETs M101 and M102 are connected to a pair of input terminals T101 and T102, respectively. A first input voltage V.sub.1 is differentially applied across the gates of the MOSFETs M101 and M102 through the pair of input terminals T101 and T102 The polarity of the voltage V.sub.1 is defined as positive when the electrical potential at the terminal T101 is higher than that at the terminal T102.
Diode-connected p-channel MOSFETs M105 and M107 are connected to the MOSFETs M101 and M102 as their loads, respectively. A gate and a drain of the MOSFET M105 are coupled together to be connected to a drain of the MOSFET M102. A source of the MOSFET M105 is connected to a power supply (not shown) providing a supply voltage V.sub.DD. A gate and a drain of the MOSFET M107 are coupled together to be connected to a drain of the MOSFET M101. A source of the MOSFET M107 is connected to the power supply.
A second differential pair is formed by n-channel MOSFETs M103 and M104 whose sources are coupled together. The gate-width (W) to gate-length (L) ratio (W/L) of the MOSFETs M103 and M104 are the same and therefore, the second differential pair is also a balanced source-coupled transistor pair.
The coupled sources of the MOSFETs M103 and M104 are connected to a terminal of a constant current sink 112 sinking the same constant current I.sub.0 as that of the constant current sink 111. The other terminal of the current sink 112 is connected to the ground. The second differential pair of the MOSFETs M103 and M104 is driven by the same constant current I.sub.0 as that of the first differential pair.
A gate and a drain of the MOSFET M103 are coupled together, the MOSFET M103 has a diode-connection. The coupled gate and drain of the MOSFET M103 are connected to an output terminal T103. An output voltage V.sub.0 is derived from the coupled gate and drain of the MOSFET M103 through the output terminal T103. The polarity of the voltage V.sub.0 is defined as positive when the electrical potential at the terminal T103 is higher than that at the ground.
A gate of the MOSFET M104 is connected to an input terminal T104. A second input voltage V.sub.2 is applied to the gate of the MOSFET M104 through the input terminal T104. The polarity of the voltage V.sub.2 is defined as positive when the electrical potential at the terminal T104 is higher than that at the ground.
A p-channel MOSFET M106 is connected to the MOSFET M103 as its load. A drain of the MOSFET M106 is connected to the coupled drain and gate of the MOSFET M103. A source of the MOSFET M106 is connected to the power supply. A gate of the MOSFET M106 is connected to the coupled gate and drain of the MOSFET M105 in the first differential pair, thereby constituting a current mirror circuit. This current mirror circuit makes a drain current of the MOSFET M102 to be equal to a drain current of the MOSFET M103.
A diode-connected p-channel MOSFET M108 is connected to the MOSFET M104. A gate and a drain of the MOSFET M108 are coupled together to be connected to a drain of the MOSFET 104. A source of the MOSFET M108 is connected to the power supply.
The diode-connected MOSFETs M107 and M108 are inserted for the purpose of making the voltages at the drains of the MOSFETs M101 and M104 equal with those at the drains of the MOSFETs M102 and M103. Thus, the operating characteristic matching for the first and second differential pairs is improved.
Ignoring the channel-length modulation and the body effect, and supposing the square-law characteristic between a drain current I.sub.D of a MOSFET and a gate-to-source voltage V.sub.GS thereof, the drain current I.sub.D and the gate-to-source voltage V.sub.GS have, in general, the following relationships (8a) and (8b). ##EQU3##
In the equation (8a), .beta. is the transconductance parameter and V.sub.TH is the threshold voltage of a MOSFET. The transconductance parameter .beta. is expressed as .mu.(C.sub.ox /2) (W/L), where .mu. is the effective carrier mobility, C.sub.ox is the gate-oxide capacitance per unit area, and W and L are a gate-width and a gate-length of a MOSFET, respectively.
Accordingly, drain currents I.sub.D1, I.sub.D2, I.sub.D3, and I.sub.D4 of the MOSFETs M101, M102, M103, and M104 are expressed as the following equations (9), (10), (11), and (12), respectively. ##EQU4##
Since the drain of the MOSFET M102 is connected to the drain of the MOSFET M103 through the current mirror circuit formed by the MOSFETs M105 and M106, the following equation (13) is established. EQU I.sub.D2 =I.sub.D3 ( 13)
The equation (13) means that the right side of the equation (10) is equal to the right side of the equation (11), resulting in a relationship of V.sub.1 =V.sub.2 -V.sub.0.
Consequently, the following equation (14) is obtained. EQU V.sub.0 =-V.sub.1 +V.sub.2 ( 14)
The equation (14) indicates that the output voltage V.sub.0 is equal to the difference of the first and second input voltages V.sub.1 and V.sub.2. Thus, it is seen that the circuit shown in FIG. 2 has a function of subtracting the first input voltage V.sub.1 from the second input voltage V.sub.2.
Unlike the equation (7), the polarity of the first input voltage V.sub.1 is negative in the equation (14). This is because the MOSFET M105 is not connected to the MOSFET M101 but the MOSFET M102. The polarity of the first input voltage V.sub.1 may be readily turned to be positive by replacing the MOSFET M105 with the MOSFET M107. Therefore, it is seen that the circuit shown in FIG. 2 may be changed to a voltage adder circuit.
A voltage adder circuit and a voltage subtractor circuit form essential and frequently-used functional blocks in analog signal processing. Especially, in recent years, the need for a voltage adder/subtractor circuit that is operable at a possibly-low supply voltage and superior in frequency characteristic has been becoming stronger and stronger. From this viewpoint, the above-described conventional voltage adder and subtractor circuits in FIGS. 1 and 2 have the following problems.
Specifically, with the conventional voltage adder and subtractor circuits shown in FIGS. 1 and 2, a signal current is supplied from the first differential pair to the second differential pair through the current mirror circuit formed by the pnp bipolar transistors Q105 and Q106 or p-channel MOSFETs M105 and M106, respectively. As a result, the linear range of the frequency characteristic is unsatisfactorily narrow.
Moreover, with the conventional bipolar voltage adder circuit shown in FIG. 1, the voltages need to be approximately equal at the collectors of the transistors Q101, Q102, Q103, and Q104 forming the first and second differential pairs for the purpose of matching the operations of the first and second differential pairs. For this reason, the power supply voltage V.sub.cc is required to be considerably high.
For example, if each of the constant current sinks 101 and 102 is composed of a simplest current mirror circuit including only two bipolar transistors, it has the inter-terminal voltage of at lowest 0.2 V. Also, each of the transistors Q101, Q102, Q103, Q104, Q105, Q106, Q107, and Q108 typically has the base-to-emitter voltage of approximately 0.7 V. Therefore, the power supply voltage V.sub.cc needs to be approximately 1.6 V (=0.7+0.7+0.2) at lowest.
Similarly, with the conventional MOS voltage subtractor circuit shown in FIG. 2, the voltages need to be approximately equal at the drains of the MOSFETs M101, M102, M103, and M104 forming the first and second differential pairs for the purpose of matching the operations of the first and second differential pairs. For this reason, the power supply voltage VDD is required to be considerably high.